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Integrating Data and Control Planes for Physical AI Workloads: Why the MIPS I8500 Matters
As AI expands beyond the cloud into the physical world, the silicon foundations that enable machines to sense, think, act, and communicate must evolve. Physical AI applications—ranging from autonomous vehicles and robotics to communications infrastructure and smart storage—depend on real-time data movement and deterministic response. Traditional architectures divide these tasks between control-plane CPUs and data-plane accelerators, creating latency, inefficiency, and integration overhead.
This HyperFRAME Research paper, sponsored by MIPS, examines how the MIPS I8500—a fully featured, RISC-V–based processor IP—unifies control and data-plane processing for next-generation Physical AI systems. Drawing on a microarchitecture lineage proven in high-volume deployments at Mobileye, the I8500 introduces four-thread-per-core efficiency, flexible memory topology, and cluster scalability up to 384 cores. Built on GlobalFoundries’ CMOS process and supported by the Atlas Explorer virtual platform, it brings foundry-scale validation and software/hardware co-design to open-standard compute.
Key Takeaways
Integrated Data and Control Planes:
The I8500 merges event-driven control logic with high-throughput data movement in a single programmable architecture—reducing latency and simplifying system design for communications, storage, and embedded AI infrastructure.
Proven Lineage, Modernized for RISC-V:
As the third generation of MIPS’s data-movement microarchitecture, the I8500 builds on silicon deployed at Mobileye while evolving to a native RISC-V implementation with standard toolchains and Linux, RTOS, and bare-metal support.
Efficiency and Scalability for Physical AI:
Four hardware threads per core, up to six cores per cluster, and 64 clusters per system deliver exceptional throughput per mm² of silicon—ideal for match-processing and data-orchestration workloads.
Design Freedom with Foundry Credibility:
MIPS’s integration with GlobalFoundries enables rapid silicon validation through monthly shuttles, accelerating time-to-market and ensuring industrial-grade reliability for automotive, industrial, and aerospace applications.
Strategic Insight:
Physical AI requires architectures that combine deterministic performance, programmability, and ecosystem maturity. The MIPS I8500 demonstrates how RISC-V at Foundry Scale can deliver that balance—bridging open innovation and enterprise-class execution.
Stephen Sopko | Analyst-in-Residence – Semiconductors & Deep Tech
Stephen Sopko is an Analyst-in-Residence specializing in semiconductors and the deep technologies powering today’s innovation ecosystem. With decades of executive experience spanning Fortune 100, government, and startups, he provides actionable insights by connecting market trends and cutting-edge technologies to business outcomes.
Stephen’s expertise in analyzing the entire buyer’s journey, from technology acquisition to implementation, was refined during his tenure as co-founder and COO of Palisade Compliance, where he helped Fortune 500 clients optimize technology investments. His ability to identify opportunities at the intersection of semiconductors, emerging technologies, and enterprise needs makes him a sought-after advisor to stakeholders navigating complex decisions.