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Is Physical AI the Market That Makes MIPS Impossible to Ignore?
ARC acquisition, ForwardEdge aerospace win, INOVA robotics platform, and Green Hills safety SDK frame MIPS as an embedded Physical AI contender
04/14/2026
Key Highlights
- Over just the past few months, the combined GF and MIPS value proposition now explicitly spans IP, custom silicon, differentiated process technology, and volume manufacturing, pointing toward a vertically integrated embedded AI platform rather than a component-level licensing business
- ForwardEdge ASIC, a wholly owned subsidiary of Lockheed Martin, selected the MIPS S8200 RISC-V NPU for an upcoming autonomous mission-critical ASIC in aerospace and defense, the most consequential program endorsement in MIPS' recent history
- GlobalFoundries announced a definitive agreement to acquire Synopsys' ARC Processor IP Solutions business, encompassing ARC-V, ARC-Classic, ARC VPX-DSP, and ARC NPX NPU product lines, at the same moment Synopsys narrowed its IP strategy toward interface and foundation IP
- MIPS and INOVA Semiconductors unveiled a robotics control reference platform for humanoids and Physical AI edge platforms, manufactured on GF's FDX process, combining RISC-V compute with INOVA's APXpress interface supporting up to 32 Gbps at up to 500 independent data channels
- MIPS and Green Hills Software announced a jointly developed Safety SDK targeting ASIL-D / SIL 3/4 certification workflows for the M8500, spanning motor control, traction inverters, battery management, and industrial robotics
The News
At Embedded World 2026, MIPS, a GlobalFoundries company, articulated a combined Physical AI platform proposition spanning processor IP, custom silicon, differentiated process technologies, and volume manufacturing. That narrative arrives alongside two product-level announcements: a robotics control reference platform developed with INOVA Semiconductors on GF's FDX process, and a Safety SDK collaboration with Green Hills Software targeting ASIL-D / SIL 3/4 certification for automotive and industrial embedded applications. Those Embedded World releases followed earlier structural moves: unveiling of the MIPS S8200 RISC-V NPU, which drew ForwardEdge ASIC, a Lockheed Martin subsidiary, as a named mission-critical aerospace and defense customer; along with GF's announcement of a definitive agreement to acquire Synopsys' ARC Processor IP Solutions business to broaden the combined processor IP portfolio. Taken together, these four events from December 2025 through March 2026 represent a transition from MIPS as an open-ISA licensor toward MIPS as a vertically integrated embedded Physical AI platform. Read the full GF executive Q&A here.
Analyst Take
The semiconductor industry has a habit of confusing architecture announcements with platform plays. When MIPS re-emerged as a RISC-V licensor, the reflexive take was: another open-ISA entrant in a crowded field, competing on ideology against a deeply entrenched Arm. We did not share that read. What we observe across the first quarter of this year is a company methodically assembling the components that separate interesting processor IP from a commercially deployable embedded system platform. The distinction matters enormously to buyers in automotive, industrial, aerospace and defense. Those procurement teams do not buy architectures (or open ideologies.) They buy certified pathways, named application ecosystems, and reliable supply chains. The read on MIPS is not that it will replace Arm in the near term. It is that MIPS is building directly into the category Arm is evolving around as their data center focus sharpens. The MIPS play is towards deterministic, safety-critical, mixed-criticality embedded compute. The company seems to be taking openness as table stakes and building beyond it into a genuine procurement advantage as European and U.S. customers seek silicon level supply chain diversity combined with sovereignty.
What Was Announced
The evidence accumulates across a set of releases spanning the last 6 months, indicating that the arc is deliberate rather than coincidental.
At CES in January, MIPS unveiled the S8200, a software-first RISC-V NPU now sampling to lead customers developing autonomous edge transportation, robotics, and embedded platforms. The S8200 is designed to support transformer and agentic language AI models at the edge, with multimodal capabilities spanning vision, radar, and speech neural networks. Silicon reference platforms are expected to sample in 2027. The key detail, however, was the disclosure that ForwardEdge ASIC selected the S8200 for an upcoming high-performance ASIC aimed at autonomous platforms. ForwardEdge ASIC is a wholly-owned, commercially focused subsidiary of Lockheed Martin and a leader in trusted microelectronics for mission-critical applications in aerospace, defense, and high-reliability industries. A Lockheed subsidiary selecting a processor IP for a program of record indicates rigorous qualification. Program signal, not a marketing validation.
Nine days later, GF announced a definitive agreement to acquire Synopsys' ARC Processor IP Solutions business, encompassing the ARC-V, ARC-Classic, ARC VPX-DSP, and ARC NPX NPU product lines, along with ASIP Designer and ASIP Programmer tooling and their associated engineering teams. Those assets are intended to integrate with MIPS upon closing, expected in the second half of 2026. Synopsys simultaneously stated it is narrowing its IP portfolio toward interface and foundation IP, effectively exiting this processor-IP segment on a strategic basis. That exit reflects the reality that design and certification costs are rising across the embedded IP segment, compressing returns for vendors without foundry or manufacturing integration to offset them. The Synopsys move reflects a broader consolidation dynamic in which standalone processor IP licensing is becoming increasingly difficult to sustain as a business model at scale.
At Embedded World, two more announcements dropped on the same day. MIPS and INOVA Semiconductors announced a robotics control reference platform for advanced humanoids and Physical AI edge platforms, combining the M8500 and S8200 RISC-V IP with INOVA's APXpress interface and GF's FDX process for ultra-low power operation, delivered as a custom SoC for mixed-criticality workloads. It is widely acknowledged that for years, European automotive OEMs have been evaluating RISC-V for domain controllers and zonal architectures. This trend seems to be accelerating as supply chain diversification and open standards adoption become procurement priorities. The MIPS and INOVA platform targets that evolving space with a GF FDX-manufactured custom SoC positioned for both humanoid robotics and automotive zonal compute. Separately, MIPS and Green Hills Software announced a jointly developed Safety SDK for the M8500. This announcement aims to enable ASIL-D and SIL 3/4 certification workflows for motor control, traction inverters, battery management, and industrial robotics. The companies plan to integrate Green Hills' MULTI toolchain, Optimizing C/C++ Compilers, and the µ-velOSity RTOS. This is in a space where Arm's Cortex-R and Cortex-M families remain the incumbent safety-certified choice in automotive microcontrollers, with years of production validation and deep ecosystem inertia behind them. Against that, the Green Hills collaboration positions MIPS not at the ISA level, where debates about openness rarely move procurement decisions, but at the workflow and certification level. This jointly developed, ASIL-D-capable SDK has the potential to remove one of the most practical barriers to program qualification and offer optionality in a space that's been lacking it.
Market Analysis
The strategic read here is vertical integration way beyond the ISA differentiation narrative. Arm's licensing model is powerful precisely because it is horizontal: Arm supplies processor IP, and a widely established ecosystem does the rest. The challenge for embedded buyers in automotive and industrial segments is that this ecosystem model increasingly requires managing fragmented supply chains across separate IP vendors, toolchains, foundries, and certification bodies. All this right at an inflection point where program complexity and certification requirements are rising in parallel. What GF and MIPS seem to be constructing is a compressed version of that stack via a customer engagement model that bridges: IP, software enablement, safety-certified development tools, differentiated process technology, and volume manufacturing.
According to our view of industrial embedded markets, we see high-consequence procurement teams increasingly favor vendors who can reduce integration friction across the full development and certification pathway versus optimizing a single layer. The GF and MIPS combined proposition, as Sameer Wasson described, aims to allow customers to "get to working silicon faster and tailor it to real-world edge AI," with GF able to build and manufacture custom silicon when standard off-the-shelf solutions do not meet program requirements. MIPS is not making an IP licensing pitch, the company is arching towards a design-to-volume service proposition.
The acquisition of Synopsys' ARC business strengthens this argument materially. Synopsys did not exit the processor IP segment because the market was contracting. Synopsys exited because it is concentrating on interface and foundation IP where its competitive advantages are most defensible. The other reason was that the economics of standalone embedded processor IP licensing are deteriorating as design costs rise and the value of vertical integration compounds. The advantage to GF and MIPS of that strategic retreat is a combination of high-performance, mid-range, and ultra-low power compute and AI cores, alongside its existing RISC-V foundation, without displacing any of the foundry revenue that makes GF's model work. The ForwardEdge aerospace and defense selection, the INOVA robotics reference platform, and the Green Hills safety SDK are not coincidental announcements. They represent MIPS systematically populating the application-specific proof points that make a platform story credible to embedded buyers across three market segments with the highest processor IP switching costs in the industry.
Looking Ahead
HyperFRAME will be monitoring two developments closely as this thesis evolves. First, integration velocity and tightness. We are going to be watching how the GF acquisition of Synopsys' ARC Processor IP Solutions business closes on the expected second-half 2026 timeline, as well as how cleanly MIPS integrates those engineering teams and product lines without disrupting existing ARC licensees. In this space, integration risk is real, and any disruption to that installed base could slow GF's path to the expanded processor IP portfolio central to the Physical AI strategy. Second, and more revealing over the longer term, will be whether the ForwardEdge aerospace and defense ASIC program translates into additional mission-critical program wins. A&D is not a market segment known for rapid decision making, instead rewarding patient and reliable ecosystem vendors over years. Beyond that segment, the timeline implications of the Green Hills Safety SDK collaboration reinforce this patience requirement. Because ASIL-D and SIL 3/4 certification processes typically require 18 to 36 months of development and validation. The early-access customer engagement noted in the Green Hills announcement suggests MIPS aims at production-ready programs well into the 2027-2028 timeframe. Aerospace and defense procurement decisions are watched closely by industrial and automotive procurement teams that value demonstrated program qualification above almost all other signals. A strong ForwardEdge production outcome, arriving around the same period those automotive safety certifications may be approaching completion, could create a compounding credibility effect that advances the platform thesis considerably faster than the individual milestones would suggest in isolation.
Stephen Sopko | Analyst-in-Residence – Semiconductors & Deep Tech
Stephen Sopko is an Analyst-in-Residence specializing in semiconductors and the deep technologies powering today’s innovation ecosystem. With decades of executive experience spanning Fortune 100, government, and startups, he provides actionable insights by connecting market trends and cutting-edge technologies to business outcomes.
Stephen’s expertise in analyzing the entire buyer’s journey, from technology acquisition to implementation, was refined during his tenure as co-founder and COO of Palisade Compliance, where he helped Fortune 500 clients optimize technology investments. His ability to identify opportunities at the intersection of semiconductors, emerging technologies, and enterprise needs makes him a sought-after advisor to stakeholders navigating complex decisions.