Can a Fabless Designer Like Broadcom Reshape EPIC’s Innovation Map?

The competitive backdrop for this announcement is the increasingly fierce battle for advanced packaging capacity. Broadcom holds approximately 15 percent of TSMC's CoWoS allocation for 2026 according to industry reporting, second only to NVIDIA's commanding share, which provides context for why Broadcom would invest engineering attention upstream at the equipment R&D layer. With Morgan Stanley projecting global CoWoS wafer demand to reach roughly 1 million units by 2026, every architectural decision made at the package level has downstream consequences for capacity allocation, yield, and time to market. By participating in EPIC, Broadcom gains visibility into Applied's deposition, lithography, etch, and electrochemical deposition roadmaps several years ahead of the time those tools land in TSMC's AP6, AP7, or AP8 facilities, or in the OSAT facilities (Amkor and SPIL) where overflow CoWoS work is being outsourced.

For Applied, today's announcement closes a meaningful gap in the EPIC ecosystem. Until now, the program has been built on visibility into supply-side roadmaps. Direct customers of Applied. Adding a fabless system designer means Applied gains a window into the architectural choices being made by the world's largest custom AI silicon design house. With that understanding, Applied can position itself when packaging tools are assessed for tool-of-record positions in the foundries and OSATs that serve Broadcom's customers. According to McKinsey's analysis of the advanced packaging opportunity, co-development across the value chain is identified as a primary mechanism for accelerating commercialization. The Broadcom tie-up applies that framing in a way the founding member roster could not, because TSMC's view of next-generation packaging is filtered through its current process recipes, while Broadcom's view originates with the system architecture itself.

The contrast with last week's TSMC announcement underscores how deliberate Applied appears to be in differentiating these collaboration models. TSMC joined as a founding partner with full (potential) co-located engineering presence, building on what Applied characterized as more than three decades of bilateral history. The focus of that engagement centers on materials engineering and process integration for advanced logic scaling across data center and edge applications. Broadcom enters as an innovation partner with access to R&D outputs across Applied's global innovation centers, so the focus is narrower and more specific: advanced packaging for AI accelerators. The same Applied executive, Dr. Prabu Raja, anchored both announcements, and that consistency suggests Applied is consciously building two parallel collaboration tracks. One track gives chipmakers cleanroom co-location and node-spanning visibility. The second track gives system designers earlier sight lines into the foundational packaging innovations that will eventually flow through whichever foundry their volume eventually lands in. Whether those tracks remain distinct or eventually merge will be one of the more interesting governance questions to watch as the EPIC roster expands.

A second competitive consideration is the panel-level packaging trajectory. Broadcom's 3.5D platforms are already pushing the limits of what 300-millimeter wafer-based CoWoS economics can sustain. The industry's possible migration toward rectangular panel substrates (510 by 515 millimeters and beyond) directly supports Broadcom's package size roadmap, and Applied's recently announced NEXX acquisition delivers panel-level electrochemical deposition capability into the same EPIC environment. The Broadcom collaboration could function, in part, as a pull-through mechanism for the panel-level tooling that Applied has been quietly assembling over the past several quarters.