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Sovereign Supply Chain as the Post-Quantum Cryptography Sales Pitch?
SEALSQ leans on GF's manufacturing scale for PQC and cryo-CMOS, betting sovereign narrative and pre-certification beat pure software plays.
7/13/2026
Key Highlights
- SEALSQ and GlobalFoundries signed a strategic Memorandum of Understanding to co-develop secure semiconductor platforms spanning post-quantum cryptography and semiconductor-based quantum computing technologies.
- Working with MIPS by GF, the partners plan to co-develop pre-certified PQC security IP hard macro blocks and Chiplet Hardware Security Module components targeted at hardware security modules and secure enclaves.
- A second workstream extends into cryoelectronic ASIC design for quantum computing systems, built on GF's Quantum Technology Solutions business and SEALSQ's quantum ASIC ambitions.
- The companies frame the pact around European and U.S. sovereign, trusted, and traceable semiconductor supply chain priorities.
- The agreement is non-binding. No capacity commitment, volume target, or delivery date accompanies either workstream.
The News
SEALSQ and GlobalFoundries announced a strategic Memorandum of Understanding to co-develop secure semiconductor platforms across post-quantum cryptography and quantum computing technologies, pairing GF's fabrication scale with SEALSQ's certified-security IP. The deal lands as enterprises face compounding pressure from crypto-agility mandates and harvest-now-decrypt-later exposure, though it commits neither side to volume or timing. The signal that matters most is architectural: security embedded at the hard macro level rather than patched in software after the fact. Full release: https://www.globenewswire.com/news-release/2026/07/08/3324047/0/en/SEALSQ-and-GlobalFoundries-Partner-to-Accelerate-Post-Quantum-Cryptography-and-Quantum-Computing-Technologies.html
Analyst Take
Every PQC announcement this year claims to move security "into the silicon." Most still mean firmware. This one is different in ambition, if not yet in proof. GlobalFoundries and SEALSQ are proposing pre-certified hard macro blocks, IP that ships already carrying its compliance credentials, rather than software libraries bolted onto an existing part number. Great idea, but the skepticism writes itself: MoUs are cheap, this one specifies no fab node, no volume, no date, and SEALSQ's market capitalization is a rounding error next to GF's. But dismissing it purely on those grounds undersells what pre-certification actually buys a customer. The idea serves up the opportunity for a shorter path through regulatory approval, often the real bottleneck standing between a quantum-safe design and a shipping product.
What Was Announced
The MoU splits into three workstreams. First, expanding GF's IP ecosystem with certified PQC security building blocks, developed alongside MIPS, targeting hardware security modules and secure enclaves. Second, advancing cryogenic CMOS technology for quantum computing, building on GF's recently announced Quantum Technology Solutions business and SEALSQ's quantum ASIC design work, aimed at cryoelectronic ASICs for joint clients and partners. Third, a sovereign-supply-chain framing tying both workstreams to European and U.S. objectives around trusted, traceable production.
SEALSQ CEO Carlos Moreira described semiconductors, cybersecurity, PQC, and quantum computing as converging into a single technology ecosystem, while GF's Nicholas Sergeant framed the work as building trusted digital infrastructure for the quantum era. Neither statement commits to a fabrication node, a unit volume, or a delivery window, and that absence is the tell. The PQC IP workstream appears the more tractable of the two: hard macro blocks are a known GF product category, and MIPS brings processor IP integration experience GF already owns. The cryo-CMOS workstream is at an earlier stage. Cryoelectronic ASICs for quantum control are still largely research-grade parts, produced in small runs for specific qubit architectures rather than a general-purpose commercial catalog item.
Market analysis
GF and SEALSQ are not entering an empty field. IBM has advanced cryo-CMOS control electronics development alongside its Heron processor family (including 156-qubit variants), and Intel's Horse Ridge chipset has run cryo-CMOS qubit control in-house for several generations. Both are vertically integrated efforts, designed by the same company that builds the qubits they control. GF and SEALSQ are proposing something closer to a merchant model, foundry-plus-fabless, for a technology category incumbents have so far kept captive. Whether that model can compete on integration depth is the open question this partnership will have to answer.
On the PQC silicon side, the field is more crowded and further along. STMicroelectronics, Samsung, and Infineon have all introduced PQC hardware accelerators in 2026, targeting connected devices and industrial microcontrollers rather than enterprise HSMs. This gives GF and SEALSQ's enterprise-security and secure-enclave positioning a reasonably clear lane rather than a head-on collision. That positioning also aligns with where advisory-led demand is building, as consulting firms have begun standing up dedicated PQC risk-assessment practices for enterprise and private equity clients, a sign the market is maturing past pure algorithm standardization into implementation and compliance tooling.
Looking Ahead
Based on what we are observing, the PQC hardware category is bifurcating into two speeds. Pre-certified IP blocks targeting HSMs and secure enclaves look like a near-term, fundable product line, since GF and MIPS already operate in adjacent IP categories. Cryo-CMOS for quantum control looks like a multi-year research bet competing against captive programs at vertically integrated incumbents that have a head start measured in silicon generations, not months. Regulatory timing adds pressure to the near-term workstream in particular: NIST-aligned crypto-agility mandates are pushing federal and defense buyers toward inventoried, migration-ready cryptography on a fixed schedule. Pre-certified hardware that shortens compliance review stands to benefit from that calendar whether or not this specific MoU is the vehicle. We will be watching for the first concrete design win or customer name attached to the PQC workstream, which would be the clearest signal this MoU is converting into revenue rather than remaining a strategic marker. On the cryo-CMOS side, the more useful catalyst is a published performance benchmark, since claims of quantum-era relevance are cheap until measured against gate fidelity and thermal load numbers the incumbents have already put on the record.
Stephen Sopko | Analyst-in-Residence – Semiconductors & Deep Tech
Stephen Sopko is an Analyst-in-Residence specializing in semiconductors and the deep technologies powering today’s innovation ecosystem. With decades of executive experience spanning Fortune 100, government, and startups, he provides actionable insights by connecting market trends and cutting-edge technologies to business outcomes.
Stephen’s expertise in analyzing the entire buyer’s journey, from technology acquisition to implementation, was refined during his tenure as co-founder and COO of Palisade Compliance, where he helped Fortune 500 clients optimize technology investments. His ability to identify opportunities at the intersection of semiconductors, emerging technologies, and enterprise needs makes him a sought-after advisor to stakeholders navigating complex decisions.