Research Notes

Does Core Count Tell CIOs and CFOs Anything Useful About Agentic AI?

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Does Core Count Tell CIOs and CFOs Anything Useful About Agentic AI?

A proposed new metric counts completed agent work per dollar, watt and rack, and lands while MLPerf builds its own agentic yardstick.

8/24/2026

Key Highlights

  • Intel proposes "delivered agents per rack" as the unit of account for agentic infrastructure, defined as theoretical agents per rack multiplied by routing efficiency, resource balance and offload efficiency.
  • The piece cites a public analysis of 739 anonymized Claude Code conversations in which CPU-side processing and wait time rose from less than 1% of total latency at a single request to as much as 15% at 32 concurrent requests, with most of the increase attributed to scheduling and queueing rather than computation.
  • The same research estimates that GPUs perform useful work during only 50% to 60% of wall-clock time in code-execution agent workflows, a figure Intel uses to argue that host-side stalls reach the most expensive silicon in the rack.
  • Supporting evidence points to Xeon 6 Flat Memory Mode, which in a joint Intel and SAP evaluation delivered 96% of all-DDR5 performance at roughly 25% lower memory total cost of ownership, and to Intel IAA snapshot compression showing approximately 1.2x faster completions.
  • Our read: the framework is architecturally self-interested by construction, and it is also the first vendor proposal we have seen that asks the industry, Intel included, to publish the losses between theoretical and delivered capacity.

The News

Intel published an opinion piece by Karin Eibschitz Segal arguing that agentic AI infrastructure should be measured by the work it reliably completes rather than by the capacity that goes into the rack, and proposing "delivered agents per rack" as the metric. The argument rests on concurrency: once many agents contend for CPU, memory, I/O and accelerator resources, scheduling and queueing appear to consume a growing share of end-to-end latency, and accelerators idle while the host waits on databases, retrieval systems and sandboxes. Intel pairs the framing with Xeon 6 capabilities aimed at keeping session state resident and moving infrastructure work off general-purpose cores, and says it intends to report agents per rack at a stated p99 latency target on real agentic traces. An accompanying white paper, How Many Agents Will Your Rack Actually Run, sets out the methodology.

Analyst Take

A port is not judged by how many cranes it owns. It is judged by containers moved before the ship leaves. That is the argument Intel is making about agentic infrastructure, and it arrives at a moment when nearly every CPU vendor is publishing rack-scale claims built on the inputs side of the ledger. The obvious objection is that a metric containing an "offload efficiency" term was designed by a company that ships QuickAssist, Data Streaming Accelerator and In-Memory Analytics Accelerator, and that competitors carrying different fixed-function blocks would weight the equation differently. That objection is fair, and we would raise it in any client briefing. It is also incomplete. The formula is falsifiable, it requires disclosure of concurrency and latency targets, and Intel applies that disclosure standard to its own numbers explicitly. Vendor-authored metrics usually hide the loss terms. This one names them.

What was Announced

The substance here is a measurement framework rather than a product. Intel defines delivered agents per rack as theoretical capacity discounted by three efficiency factors: how well work is placed, how much is lost to bottlenecks and queueing, and how much core capacity is recovered by offloading infrastructure tasks. The claimed insight is that the binding constraint sits where the latency curve crosses the customer's target, not at the top of a throughput chart, which is a familiar idea in database and storage engineering and a comparatively new one in AI infrastructure marketing.

The supporting evidence is where the piece earns attention. In the cited analysis of coding-agent traces, CPU-side processing and wait time climbed toward 15% of total latency at 32 concurrent requests from a starting point below 1%, and the increase is attributed largely to scheduling and queueing. Faster cores do not dissolve queues. The second figure, GPUs doing useful work during roughly 50% to 60% of wall-clock time in code-execution agent flows, is the one CIOs and CFOs should obsess over, because it converts a scheduling problem into a capital utilization problem.

Intel's product mapping follows predictably. Flat Memory Mode combines CXL-attached memory and native DDR5 in a single address space, positioned as a way to keep more sessions warm without an all-DDR5 bill. The fixed-function accelerators are framed as capacity returned rather than features shipped. The P-core and E-core portfolio is presented as a placement mechanism, letting orchestration, tool execution and state movement land on different execution profiles. Crescent Island is acknowledged as the accelerator half of the story, though the piece is careful to keep the emphasis on the host. Notably, the source analysis is described as public but is not named, which we would want cited before quoting the figures in a client deliverable.

Market Analysis

The measurement debate is now the competitive debate. Intel and partners showed rack blueprints packing 36,864 CPU cores into a 100 kW envelope at Computex, and Arm has promoted reference designs reaching 45,696 cores in a liquid-cooled rack. Those are input figures, and Intel's own participation in that genre is precisely what makes this opinion piece interesting: the company is arguing against a scoreboard it has been playing on.

AMD has built its agentic case on rack-level throughput across the transactional, web-serving and middleware tiers that surround agent systems, reasoning that concurrency per rack governs how many agents an environment sustains. NVIDIA has argued a different design point around per-core performance and predictable loaded latency for tool execution and code analysis. Each framing is internally coherent, and each maps cleanly onto the architecture its author ships. That is not a criticism. It is what happens when a workload category outruns its benchmarks.

The resolution is already underway, and it is the context the Intel piece leaves out. MLCommons added an Agentic Inference track to MLPerf in July, co-built with AMD, Intel, NVIDIA and Workato, covering multi-turn coding and enterprise workflow trajectories under growing context. MLPerf Endpoints and the agentic categories in MLPerf Client v2.0 extend the same effort across serving and client tiers. Independent harness work, including ServeTheHome's agentic rack testing, is applying scrutiny to vendor-defined agentic benchmarks in parallel.

So the strategic question is not whether Intel's metric is better than the alternatives. It is whether "delivered agents per rack" gets absorbed into the neutral standard or remains a house measure. Our read is that the loss-factor decomposition is the durable contribution, and the branded metric is the less durable part.

Looking Ahead

The key trend we'll be monitoring is whether Intel publishes against its own standard before the standard bodies do it for the industry. The company has committed to reporting agents per rack at a stated p99 target on real agentic traces, along with routing efficiency, offload gains, host efficiency in GPU-attached systems and agents per watt under a defined rack power constraint. That is a demanding disclosure list. Meeting it would give buyers something they currently lack, which is a way to compare hosts on completed work rather than on core count and TDP. Falling short would reduce the framework to positioning. We will also watch how the MLPerf agentic tracks handle host-side contribution, since a benchmark that measures serving systems end to end may capture the same queueing losses without needing a vendor-specific formula. Second-half deployments should tell us whether procurement language starts moving from cores to completions.

Author Information

Stephen Sopko | Analyst-in-Residence – Semiconductors & Deep Tech

Stephen Sopko is an Analyst-in-Residence specializing in semiconductors and the deep technologies powering today’s innovation ecosystem. With decades of executive experience spanning Fortune 100, government, and startups, he provides actionable insights by connecting market trends and cutting-edge technologies to business outcomes.

Stephen’s expertise in analyzing the entire buyer’s journey, from technology acquisition to implementation, was refined during his tenure as co-founder and COO of Palisade Compliance, where he helped Fortune 500 clients optimize technology investments. His ability to identify opportunities at the intersection of semiconductors, emerging technologies, and enterprise needs makes him a sought-after advisor to stakeholders navigating complex decisions.