Who Wins HBM Onshoring When The Wafers Stay Offshore?

Key Highlights

• SK hynix broke ground on 27 August at Purdue University in West Lafayette for its first US production base, an advanced packaging facility for AI memory carrying a stated investment of over $4 billion, raised from the $3.87 billion agreed in April 2024.
• The cleanroom is scheduled to open by October 2028 with mass production in the second half of 2029, roughly a year later than the second-half-2028 target attached to the original announcement, and CHIPS support was finalized in December 2024 at up to $458 million in direct funding plus up to $500 million in loan authority, following an August 2024 preliminary memo of terms for $450 million.
• Cutting-edge wafers produced in Korea will be shipped to Indiana for advanced packaging and test, after which the company describes the finished stacks as Made in USA products for US customers.
• The release cites approximately 1,000 personnel at commercial operation, roughly 7,000 direct and indirect jobs, more than 100 partners across materials, components and equipment, an MOU with Purdue on advanced packaging R&D, and an on-site R&D testbed.
• Three weeks earlier, the SK hynix board approved roughly 54.3 trillion won for two new Korean fabs, on the order of $38 billion USD, split between 35.2 trillion won for the Yongin Y2 DRAM site (roughly $25 billion) and 19.1 trillion won for the Cheongju M17 NAND site (roughly $13 billion), against a stated Yongin cluster master plan of 600 trillion won, or something near $420-$430 billion.
• The January 2026 Section 232 proclamation imposed a 25% duty on a narrow basket of advanced computing articles with broad data center end-use carve-outs, did not name memory, and directed a Commerce report on the data center semiconductor market by 1 July 2026 that has not appeared publicly as of this writing.

The News

SK hynix held a groundbreaking ceremony in West Lafayette, Indiana for what it describes as its first HBM production base in the United States, an advanced packaging and test facility representing an investment of over $4 billion. The site is designed to receive wafers fabricated in Korea, stack and package them into HBM, and ship finished modules to US customers, with cleanroom completion targeted for October 2028 and mass production for the second half of 2029. The company also signed an MOU with Purdue University covering system integration and advanced packaging research, and committed to a recruitment channel for discharged US Forces Korea service members. Full details are in the SK hynix release.

Analyst Take

The dollar figure, while substantial, is not our take from this announcement. Over $4 billion buys a serious advanced packaging line, and we do not want to minimize that. But three weeks before the announcement in Indiana, the same board approved roughly 54.3 trillion won (~ $38 billion) for two new fabs in Yongin and Cheongju, a commitment on the order of ten times larger. The comparison is not perfectly clean, since the Cheongju piece is a NAND fab rather than an HBM front end, though even the Yongin DRAM line on its own runs several times the Indiana number. Read together, the two decisions describe a company U.S.-onshoring the last step of HBM manufacturing while keeping the capital-intensive front end firmly in Korea. The bear reading writes itself: a ceremony staged with a senator and a governor, three years ahead of first output, while the second phase of US tariff policy sits unresolved, looks like a trade hedge dressed as industrial policy. That reading is fair as far as it goes. It also misses where the physical bottleneck in AI memory actually sits.

What was Announced

The facility is an advanced packaging and test operation, not a wafer fab. Korean-fabricated wafers travel to West Lafayette for stacking, interconnect and test, and the company describes the resulting product as Made in USA. That phrase is SK hynix’s, not a customs determination. Country of origin for semiconductors turns on where substantial transformation occurs, and stacking and test can satisfy that standard or fail it depending on the facts. Anyone modeling tariff exposure should treat the label as untested rather than settled.

The schedule deserves attention. The April 2024 announcement targeted mass production in the second half of 2028. The current release moves that to the second half of 2029, with the cleanroom scheduled for October 2028. At the ceremony, CEO Kwak Noh-Jung pointed to third-quarter 2029 volume on HBM4E rather than HBM4. A year of slip is not unusual on a project of this kind, given the site relocation within West Lafayette and the tightness in construction labor and electrical infrastructure across the Midwest, though we would not treat the relocation as the whole explanation. Indiana is a later-cycle packaging node.

The R&D testbed is the underappreciated element, and the Purdue MOU probably matters more as a talent instrument than as a research vehicle. Indiana’s existing semiconductor presence deserves precision here: MediaTek operates a chip design center and imec anchors a research partnership, neither of which is a packaging line. The binding constraint on US advanced packaging is packaging engineers, not packaging ideas.

Site work began in the first half of 2026, fencing in February and foundation piling in April, well ahead of the ceremony. That sequence matters more than the ribbon, because the Section 48D investment tax credit is currently set to expire for property whose construction begins after 31 December 2026, and the credit turns on a physical-work test. We offer the connection as inference rather than company statement, but the position looks secured.

Market Analysis

The three HBM suppliers have now placed three different bets on the same question. SK hynix is putting US packaging first and leaving wafers in Korea. Micron, whose US manufacturing and R&D commitment has been raised above $250 billion through 2035 from the roughly $200 billion it carried in mid-2025, has explicitly sequenced its domestic HBM advanced packaging behind sufficient DRAM wafer capacity in Idaho, meaning US wafers precede US stacking. Samsung is building substantial US capacity in Taylor, Texas, but Taylor is foundry, with HBM4 and HBM4E stack work concentrated in Korea. As far as the U.S. market looks: one company is onshoring the end of the line, one the beginning, and one is not yet onshoring memory at all.

We think the SK hynix sequencing is the more defensible near-term choice, and the reason is capital efficiency under uncertainty. Advanced packaging is the tollbooth on the AI accelerator supply chain: every stack passes through it, and there are very few lanes. A packaging line costs a fraction of a leading-edge DRAM fab, ramps faster, and can be fed by whichever wafer source is most economic at the time. That optionality matters because Phase 2 remains open. The January proclamation covered a narrow logic basket with broad data center end-use carve-outs and did not name memory, and the Commerce data center study it directed has not surfaced publicly. Separately and later, Commerce Secretary Lutnick warned that Korean and Taiwanese suppliers declining to invest domestically could face substantially higher duties. That warning, not the proclamation text, is where the memory exposure argument actually comes from, and the distinction is worth preserving.

The capital allocation picture invites its own scrutiny. SK hynix listed American Depositary Shares in the US this year, and its board recently approved a 40 trillion won share repurchase and cancellation program alongside a lift in its free cash flow return commitment. That is a shareholder return several times the size of the Indiana investment. Set against the Yongin master plan, over $4 billion in West Lafayette reads as a considered position rather than a pivot, and customers should size expectations accordingly.

Looking Ahead

The key trend we will be monitoring is whether advanced packaging becomes the standard entry point for foreign memory suppliers building in the United States. West Lafayette suggests a template: bring the back end, keep the front end, let the wafer stay a traded good. If Phase 2 arrives with an offset structure rewarding capital deployed on US soil, Indiana counts handsomely and Samsung faces pressure to announce something comparable. If eligibility keys on where the silicon started, the calculus inverts. That fork is the load-bearing question, and it is unanswered in public text. Watch three markers over the next four quarters:

• whether SK hynix names an anchor customer for Indiana output,
• whether the October 2028 cleanroom date holds through the first full construction season, and
• whether the overdue data center findings pull memory into scope.

One speculative thread is worth a thought. SK hynix published first high bandwidth flash specifications with Sandisk in early August, which hints the packaging constraint may be broadening beyond DRAM stacks, and a line built for HBM could find itself qualifying something else by 2029.